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sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc digital signal processor adsp-21160m/adsp-21160n rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. summary high performance 32-bit dspapplications in audio, medi- cal, military, graphics, imaging, and communication super harvard architecture4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-over- head i/o backward compatibleassembly source level compatible with code for adsp-2106x dsps single-instruction, multiple-data (simd) computational architecturetwo 32-bit ieee floating-point computation units, each with a multiplier, alu, shifter, and register file integrated peripheralsintegrated i/o processor, 4m bits on-chip dual-ported sram, glueless multiprocessing fea- tures, and ports (serial, link, external bus, and jtag) features 100 mhz (10 ns) core instruction rate (adsp-21160n) single-cycle instruction exec ution, including simd opera- tions in both computational units dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping and singl e-cycle loop setup, provid- ing efficient program sequencing ieee 1149.1 jtag standard test access port and on-chip emulation 400-ball 27 mm 27 mm pbga package available in lead-free (rohs compliant) package 200 million fixed-point macs sustained performance (adsp-21160n) figure 1. function al block diagram mult alu barrel shifter data register file (pey) 16 x 40-bit mult alu barrel shifter data register file (pex) 16x40-bit serial ports (2) link ports (6) 4 6 6 60 iop registers (memory mapped) control, status and data buffers i/o processor dma controller timer instruction cache 32x48-bit addr data data data addr addr data addr two independent dual-ported blocks processor port i/o port dual-ported sram jtag test and emulation 6 host port addr bus mux ioa 18 iod 64 multiprocessor interface external port data bus mux 64 32 32 pm address bus dm address bus pm data bus dm data bus bus connect (px) dag1 8x4x32 32 16/32/40/48/64 32/40/64 core processor program sequencer dag2 8x4x32 b l o c k 0 b l o c k 1
rev. b | page 2 of 60 | february 2010 adsp-21160m/adsp-21160n single-instruction, multiple-data (simd) architecture provides two computational processing elements concurrent executioneach processing element executes the same instruction, but operates on different data code compatibilityat assembly level, uses the same instruction set as the adsp-2106x sharc dsps parallelism in buses and computational units allows single-cycle execution (with or without simd) of a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory an d core at up to four 32-bit floating- or fixe d-point words per cycle accelerated fft butterfly computation through a multiply with add and subtract memory attributes 4m bits on-chip dual-ported sram for independent access by core processor, host, and dma 4g word address rang e for off-chip memory memory interface supports programmable wait state gen- eration and page-mode for off-chip memory dma controller supports 14 zero-overhead dma channels for transfers between adsp-21160x internal memory and external memory, external peripherals, host processor, serial ports, or link ports 64-bit background dma transfers at core clock speed, in parallel with full-speed processor execution host processor interface to 16- and 32-bit microprocessors multiprocessing support provides glueless connection for scalable dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus con- nect of up to 6 adsp-21160x processors plus host 6 link ports for point-to-point connectivity and array multiprocessing serial ports provide two synchronous serial port s with companding hardware independent transmit and receive functions tdm support for t1 and e1 interfaces 64-bit-wide synchronous external port provides glueless connection to asynchronous and sbsram exter- nal memories
adsp-21160m/adsp-21160n rev. b | page 3 of 60 | february 2010 table of contents summary ............................................................... 1 features ................................................................. 1 table of contents .................................................... 3 revision history ...................................................... 3 general description ................................................. 4 adsp-21160x family core architecture .................... 4 memory and i/o interface features ........................... 5 development tools ............................................... 8 designing an emulator-compa tible dsp board (target) 10 additional information ......................................... 10 pin function descriptions ........................................ 11 specifications ......................................................... 15 operating conditionsadsp-21160m . ................... 15 electrical characteristicsadsp-21160m ................. 16 operating conditionsadsp-21160n .. ................... 17 electrical characteristicsadsp-21160n . ................ 18 absolute maximum ratings ................................... 19 esd sensitivity ................................................... 19 package information ............................................ 19 timing specifications ........................................... 20 output drive currentsadsp-21160m ... ................ 47 output drive currentsadsp-21160n ... ................ 47 power dissipation ............................................... 47 test conditions .................................................. 48 environmental conditions .................................... 51 400-ball pbga pin configurations ... .......................... 52 outline dimensions ................................................ 57 surface-mount design ............................................. 57 ordering guide ..................................................... 58 revision history 2/10rev. a to rev. b corrected pin assignments in last 15 rows of table 40 ( 400-ball pbga pin assignments )............................... 52
rev. b | page 4 of 60 | february 2010 adsp-21160m/adsp-21160n general description the adsp-21160x sharc ? dsp family has two members: adsp-21160m and adsp-21160n. the adsp-21160m is fabri- cated in a 0.25 micron cmos process. the adsp-21160n is fabricated in a 0.18 micron cmos process. the adsp-21160n offers higher performance and lower power consumption than the adsp-21160m. easing port ability, the adsp-21160x is application source code compatible with first generation adsp-2106x sharc dsps in sisd (single instruction, single data) mode. to take advantage of the processors simd (single- instruction, multiple-data) capa bility, some code changes are needed. like other sharc dsps, the adsp-21160x is a 32-bit processor that is optimized fo r high performance dsp applica- tions. the adsp-21160x includes a core running up to 100 mhz, a dual-ported on-chip sram, an integrated i/o pro- cessor with multiprocessing su pport, and multiple internal buses to eliminate i/o bottlenecks. table 1 shows major differences between the adsp-21160m and adsp-21160n processors. the adsp-21160x introduces sing le-instruction, multiple-data (simd) processing. using two computational units (adsp-2106x sharc dsps have one), the adsp-21160x can double performance versus the adsp-2106x on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, low power cmos process, the adsp-21160n has a 10 ns instruction cycle time. with its simd computational hardware running at 100 mhz, the adsp-21160n can perform 600 million math operations per second (480 million oper ations for adsp-21160m at a 12.5 ns instruction cycle time). table 2 shows performance benchmarks for the adsp-21160x. these benchmarks provide single -channel extrapolations of measured dual-channel (simd) processing performance. for more information on benchmarking and optimizing dsp code for single- and dual-channel processing, see the analog devices website (www.analog.com). the adsp-21160x continues the sharc familys industry- leading standards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 4m-bit dual-ported sram memory, host processor interfac e, i/o processor that supports 14 dma channels, two serial ports, six link ports, external par- allel bus, and glueless multiprocessing. the functional block diagram ( figure 1 on page 1 ) of the adsp-21160x illustrates the follo wing architectural features: ? two processing elements, each made up of an alu, multi- plier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer wi th instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core every core proces- sor cycle ?interval timer ?on-chip sram (4m bits) ? external port that supports: ? interfacing to off-ch ip memory peripherals ? glueless multiprocessing support for six adsp-21160x sharc dsps ?host port ? dma controller ? serial ports and link ports ? jtag test access port figure 2 shows a typical single-pro cessor system. a multipro- cessing system appears in figure 5 on page 9 . adsp-21160x family core architecture the adsp-21160x processor includ es the following architec- tural features of the ad sp-2116x family core. the adsp-21160x is code co mpatible at the asse mbly level with the adsp-2106x and adsp-21161. simd computational engine the adsp-21160x contai ns two computationa l processing ele- ments that operate as a single-instruction multiple-data (simd) engine. the processing elements are referred to as pex and pey, and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is table 1. adsp-21160x sharc processor family features feature adsp-21160m adsp-21160n sram 4 mbits 4 mbits operating voltage 3.3 v i/o 2.5 v core 3.3 v i/o 1.9 v core instruction rate 80 mhz 100 mhz link port transfer rate (6) 80 mbytes/s 100 mbytes/s serial port transfer rate (2) 40 mbits/s 50 mbits/s table 2. adsp-21160x benchmarks benchmark algorithm adsp-21160m 80 mhz adsp-21160n 100 mhz 1024 point complex fft (radix 4, with reversal) 115 s 92 s fir filter (per tap) 6.25 ns 5 ns iir filter (per biquad) 25 ns 20 ns matrix multiply (pipelined) [3 3] [3 1] 56.25 ns 45 ns [4 4] [4 1] 100 ns 80 ns divide (y/x) 37.5 ns 30 ns inverse square root 56.25 ns 45 ns dma transfer rate 560m bytes/s 800m bytes/s
adsp-21160m/adsp-21160n rev. b | page 5 of 60 | february 2010 enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math-intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. in simd mode, twice the data bandwidth is required to sustain computa- tional operation in the processi ng elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processi ng elements. when using the dags to transfer data in simd mode, two data values are trans- ferred with each access of me mory or the register file. independent, paralle l computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform single-cycle instructions. the three units with in each processing element are arranged in parallel, maximizi ng computational throughput. single multifunction instruct ions execute parallel alu and multiplier operations. in si md mode, the parallel alu and multiplier operations occur in both processing elements. these computation units support ieee 32-bit single-precision float- ing-point, 40-bit extended-preci sion floating-point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined wi th the adsp-2116x enhanced harvard architecture, allow unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. single-cycle fetch of instruction and four operands the processor features an enhanced harvard architecture in which the data memory (dm) bu s transfers data, and the pro- gram memory (pm) bus transfer s both instructions and data (see the functional block diagram 1 ). with the adsp-21160x dsps separate program and da ta memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands and an instruction (fro m the cache), all in a single cycle. instruction cache the adsp-21160x includes an on -chip instruction cache that enables three-bus operation for fe tching an instruction and four data values. the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core, providing looped operations, such as digital filt er multiply- accumulates and fft butterfly processing. data address generators with hardware circular buffers the adsp-21160x dsps two data address generators (dags) are used for indirect addressing and provide for implementing circular data buffers in hardware . circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the product contain sufficient registers to a llow the creation of up to 32 cir- cular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wraparound, reducing overhead, increasing performanc e, and simplifying implemen- tation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations for concise programm ing. for example, the proces- sor can conditionally execute a mu ltiply, an add, and subtract, in both processing elements, wh ile branching, all in a single instruction. memory and i/o interface features augmenting the adsp-2116x fa mily core, the adsp-21160x adds the following architectural features. figure 2. single-processor system 3 4 reset jtag 6 ad s p-21160x bms clock link device s (6 max) (optional) cs boot eprom (optional) addr memory/ mapped device s (optional) oe data dma device (optional) data addr data ho s t proce ss or interface (optional) cs rdx page clkout ack br1C6 dmar1C2 clkin irq2C0 lxclk tclk0 rpba 4 clk_cfg 3 ?0 eboot lboot flag 3 ?0 timexp lxack lxdat7?0 dr0 dt0 r s f0 tf s 0 rclk0 tclk1 dr1 dt1 r s f1 tf s 1 rclk1 id2?0 s erial device (optional) s erial device (optional) pa redy hbg hbr dmag1C2 sbts ms3C0 wrx data6 3 ?0 data addr cs ack we addr 3 1?0 da t a c o n t ro l ad dr e s s cif br s t
rev. b | page 6 of 60 | february 2010 adsp-21160m/adsp-21160n dual-ported on-chip memory the adsp-21160x contains four megabits of on-chip sram, organized as two blocks of 2m bits each, which can be config- ured for different combinations of code and data storage ( figure 3 ). each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor. the dual-ported memory in comb ination with three separate on-chip buses allows two data tr ansfers from the core and one from i/o processor, in a sing le cycle. the adsp-21160x mem- ory can be configured as a maximum of 128k words of 32-bit data, 256k words of 16- bit data, 85k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. all of the memory can be accessed as 16-, 32-, 48-, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a sin- gle instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. in this case, the instruction must be available in the cache. off-chip memory and peripherals interface the adsp-21160x dsps external po rt provides the processors interface to off-chip memory and peripherals. the 4g word off- chip address space is included in the processors unified address space. the separate on-chip buse sfor pm addresses, pm data, dm addresses, dm data, i/o ad dresses, and i/o dataare mul- tiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits of the 64 co nnect to odd addresses. every access to external memory is based on an address that fetches a 32-bit word, and with the 64-bit bus, two address locations can be accessed at once. when fetching an instruction from external memory, two 32-bit data location s are being accessed (16 bits are unused). figure 4 shows the alignment of various accesses to external memory. the external port supports as ynchronous, synchronous, and synchronous burst accesses. zbt synchronous burst sram can be interfaced gluelessly. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select sign als. separate control lines are also generated for simplified addressing of page-mode dram. the adsp-21160x provides progra mmable memory wait states and external memory acknowledge controls to allow interfacing to dram and peripherals with variable access, hold, and disable time requirements. dma controller the adsp-21160x dsps on-chip dma controller allows zero- overhead data transfers without processor intervention. the dma controller operates indepe ndently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the processors internal memory and external memory, external peri pherals, or a host processor. dma transfers can also occur between the products dsps internal memory and its serial po rts or link ports. external bus packing to 16-, 32-, 48-, or 64- bit words is performed during dma transfers. fourteen channels of dma are available on the adsp-21160xsix via the link ports, four via the serial ports, and four via the processors external port (for either host pro- cessor, other adsp-21160x pr ocessors, memory or i/o transfers). programs can be down loaded to the processor using dma transfers. asynchronous o ff-chip peripher als can control two dma channels using dma request/grant lines (dmar1C2 , dmag1C2 ). other dma features include inter- rupt generation upon completion of dma transfers, two- dimensional dma, and dma chaining for automatic linked dma transfers. figure 3. memory map 0x00 0000 0x02 0000 0x04 0000 0x08 0000 0x10 0000 0x20 0000 0x30 0000 0x40 0000 0x50 0000 0x60 0000 0x70 0000 0x7f ffff 0x80 0000 0xffff ffff internal memory space external memory space iop reg?s long word normal word short word internal space internal space internal space internal space internal space internal space broadcast all dsps bank 0 bank 1 bank 2 bank 3 nonbanked ms 0 ms 1 ms 2 ms 3 memory (id = 011) (id = 100) memory (id = 101) memory memory (id = 110) write to (id = 111) memory (id = 010) memory (id = 001) multiprocessor memory space
adsp-21160m/adsp-21160n rev. b | page 7 of 60 | february 2010 multiprocessing the adsp-21160x offers powerful fe atures tailored to multipro- cessing dsp systems as shown in m. the external port and link ports provide integrated glueless multiprocessing support. the external port supports a unified address space (see figure 3 ) that allows direct interprocesso r accesses of each processors internal memory. distributed bus arbitration logic is included on-chip for simple, glueless conn ection of systems containing up to six adsp-21160x processors and a host processor. master processor changeover incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock allows indivisible read-m odify-write sequences for sema- phores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 400m bytes/s (adsp- 21160n) over the external port. broadcast writes allow simultaneous transmission of data to all adsp-21160x dsps and can be us ed to implement reflective semaphores. six link ports provide for a seco nd method of multiprocessing communications. each link port can support communications to another adsp-21160x. using th e links, a large multiproces- sor system can be constructed in a 2d or 3d fashion. systems can use the link ports and cluster multiprocessing concurrently or independently. link ports the processor features six 8-bit link ports that provide addi- tional i/o capabilities. with the capability of running at 100 mhz rates, each link po rt can support 100m bytes/s (adsp-21160n). link port i/o is es pecially useful for point-to- point interprocessor communication in multiprocessing sys- tems. the link ports can operate independently and simultaneously. link port data is packed into 48- or 32-bit words, and can be directly read by the core processor or dma- transferred to on-chip memory. ea ch link port has its own dou- ble-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are pro- grammable as transmit or receive. serial ports the processor features two sync hronous serial ports that pro- vide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. the serial ports can operate up to half the clock rate of the co re, providing each with a maxi- mum data rate of 50m bits /s (adsp-21160n). independent transmit and receive functions provide greater flexibility for serial communications. serial po rt data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports offers a tdm multichannel mode. the serial ports can operate with little-endian or big-endian trans- mission formats, with word lengths selectable from 3 bits to 32 bits. they offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be generated internally or externally. host processor interface the adsp-21160x host interface allows easy connection to standard microprocessor buses, bo th 16- and 32-bit, with little additional hardware required. the host interface is accessed through the adsp-21160x dsps ex ternal port and is memory- mapped into the unified address space. four channels of dma are available for the host interfac e; code and data transfers are accomplished with low software overhead. the host processor communicates with the adsp-21 160x dsps external bus with host bus request (hbr ), host bus grant (hbg ), ready (redy), acknowledge (ack), and chip select (cs) signals. the host can directly read and write the inte rnal memory of the processor, and can access the dma channel setup and mailbox registers. vector interrupt support provides efficient execution of host commands. the host processor interface can be used in either multiproces- sor or uniprocessor systems. fo r multiprocessor systems, host access to the sharc requires that address pins addr17, addr18, addr19, and addr20 be driven low. it is not enough to tie these pins to grou nd through a resistor (for exam- ple, 10 k ). these pins must be driven low with a strong enough drive strength (10 to 50 ) to overcome the sharc keeper latches present on these pins. if the drive strength provided is not strong enough, data access failures can occur. for uniprocessor sharc systems us ing this host access feature, address pins addr17, addr 18, addr19, and addr20 may be tied low (for exam ple, through a 10 k ohm resistor), driven low by a buffer/driver, or left floating. any of these options is sufficient. program booting the internal memory of the adsp -21160x can be booted at sys- tem power-up from an 8-bit eprom, a host processor, or through one of the link ports. se lection of the boot source is figure 4. external data alignment options data6 3 ?0 6 3 55 47 3 9 3 12 3 15 7 0 rdh / wrh rdl / wrl eprom 16-bit packed 3 2-bit packed 64-bit tran s . for 40-bit ext. preci s ion 64-bit tran s fer for 4 8 -bit in s truction fetch re s tricted dma, ho s t, eprom data alignment s : 64-bit long word, s imd, dma, iop regi s ter tran s fer s byte 0 byte 7 3 2-bit normal wd. (even addr.) 3 2-bit normal word (odd addr)
rev. b | page 8 of 60 | february 2010 adsp-21160m/adsp-21160n controlled by the bms (boot memory select), eboot (eprom boot), and lboot (l ink/host boot) pins. 32-bit and 16-bit host processors can be used for booting. phase-locked loop the processor uses an on-chip pll to generate the internal clock for the core. ratios of 2:1, 3:1, and 4:1 between the core and clkin are supported. the clk_cfg pins are used to select the ratio. the clkin rate is the rate at which the synchro- nous external port operates. power supplies the processor has separate powe r supply connections for the internal (v ddint ), external (v ddext ), and analog (av dd and agnd) power supplies. the intern al and analog supplies must meet the v ddint and av dd requirement. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same supply. the pll filter, figure 6 , must be added for each adsp-21160x in the system. v ddint is the digital core supply. it is recom- mended that the capacitors be connected directly to agnd using short thick trace. it is recommended that the capacitors be placed as close to av dd and agnd as possibl e. the connection from agnd to the (digital) grou nd plane should be made after the capacitors. the use of a thick trace for agnd is reasonable only because the pll is a relati vely low power circuitit does not apply to any other ad sp-21160x gnd connection. development tools the adsp-21160x is supported with a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and the visualdsp++ ? ? development environment. the sa me emulator hardware that supports other adsp-2116x processors also fully emulates the adsp-21160x. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the dsp has archi- tectural features that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the so ftware developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ integrated de velopment and debugging envi- ronment (idde) lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all of the blackfin develop- ment tools, including the colo r syntax highli ghting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. figure 6. analog power (av dd ) filter circuit ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc. 10 v ddint 0.1 f 0.01 f agnd av dd
adsp-21160m/adsp-21160n rev. b | page 9 of 60 | february 2010 figure 5. shared memory multiprocessing system addr 3 1?0 pa bms c on t ro l ad s p-21160x #1 5 pa control ad s p-21160x #2 addr 3 1?0 pa control ad s p-21160x # 3 5 id2?0 reset rpba clkin id2?0 reset rpba id2?0 reset rpba clkin ad s p-21160x #6 ad s p-21160x #5 ad s p-21160x #4 clock re s et addr data ho s tproce ss or interface (optiona ack global memory and peripheral s (optional) oe addr data cs addr data boot eprom (optio rdx ms3C0 sbts cs ack addr 3 1?0 clkin 3 001 page 3 010 3 011 br1 br2C6 redy hbg hbr cs we wrx 5 c o n t ro l a d d re s s da t a c o n t r ol a dd r e ss d a t a data6 3 ?0 br1C2 , br4C6 br3 data6 3 ?0 br1 , br3C6 br2 data6 3 ?0 bu s priority
rev. b | page 10 of 60 | february 2010 adsp-21160m/adsp-21160n because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but can also be used via standard command-line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gen- eration of various vdk-based objects, and visualizing the system state, when debugging an application that uses the vdk. use the expert linker to visua lly manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical fo rm, easily move code and data to different areas of the dsp or external memory with the drag of the mouse, examine run time stack and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the develo per to move between the graphi- cal and textual environments. analog devices dsp emulators use the ieee 1149.1 jtag test access port of the adsp-21160x processor to monitor and con- trol the target board processor during emulation. the emulator provides full-speed emulation, a llowing inspection and modifi- cation of memory, registers, an d processor stacks . nonintrusive in-circuit emulation is assured by the use of the processors jtag interfacethe emulator do es not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the adsp-2116x processor family. hardware tools include adsp -2116x processor pc plug-in cards. third-party so ftware tools include dsp libraries, real- time operating systems, an d block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set br eakpoints, obse rve variables, observe memory, and examine re gisters. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single-processor connec tions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see analog devices jtag emul ation technical reference (ee-68) on the analog devices website (ww.analog.com)use site search on ee-68. this document is updated regularly to keep pace with improvemen ts to emulator support. additional information this data sheet provides a general overview of the adsp-21160x architecture and func tionality. for detailed infor- mation on the blackfin family co re architecture and instruction set, refer to the adsp-21160 sharc dsp hardware reference and the adsp-21160 sharc dsp in struction set reference . for detailed information on the deve lopment tools for this proces- sor, see the visualdsp++ users guide .
adsp-21160m/adsp-21160n rev. b | page 11 of 60 | february 2010 pin function descriptions adsp-21160x pin definitions are li sted below. inputs identified as synchronous (s) must meet ti ming requirements with respect to clkin (or with respect to tck for tms, tdi). inputs iden- tified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). tie or pull unused inputs to v dd or gnd, except for the following: ? addr31C0, data63C0, page, brst, clkout (id2C0 = 00x) (note: these pins have a logic-level hold circuit enabled on the adsp-21160x dsp with id2C0 = 00x.) ?pa , ack, ms3C0 , rdx , wrx , cif , dmarx , dmagx (id2C0 = 00x) (note: these pins have a pull-up enabled on the adsp-21160x with id2C0 = 00x.) ? lxclk, lxack, lxdat7C0 (lxpdrde = 0) (note: see link port buffer control regi ster bit definitions in the adsp-21160 sharc dsp hardware reference .) ? dtx, drx, tclkx, rclkx, emu , tms, trst , tdi (note: these pins have a pull-up.) the following symbol s appear in the type column of table 3 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state (when sbts is asserted, or when the ad sp-21160x is a bus slave). table 3. pin function descriptions pin type function addr31C0 i/o/t external bus address. the adsp-21160x ou tputs addresses for external memory and peripherals on these pins. in a multiprocessor system, the bus master outputs addresses for read/writes of the internal memory or iop registers of other adsp-21160x dsps. the adsp-21160x inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or iop registers. a keeper latch on the dsps addr31C0 pins maintains the input at the level it was last driven (only enabled on the processor with id2C0 = 00x). data63C0 i/o/t external bus data. the adsp-21160x inputs and outputs data and instructions on these pins. pull- up resistors on unused data pins are not necessa ry. a keeper latch on the dsps data63-0 pins maintains the input at the level it was last driven (only enabled on the processor with id2C0 = 00x). ms3C0 o/t memory select lines. these outputs are asserted (low) as chip selects for the corresponding banks of external memory. memory bank size must be defined in the syscon control register. the ms3C0 outputs are decoded memory address lines. in asynchronous access mode, the ms3C0 outputs transition with the other address outputs. in synchronous access modes, the ms3C0 outputs assert with the other address lines; however, they deassert after the first clkin cycle in which ack is sampled asserted. ms3C0 has a 20 k internal pull-up resistor that is enabled on the adsp-21160x with id2C0 = 00x. rdl i/o/t memory read low strobe. rdl is asserted whenever adsp-211 60x reads from the low word of external memory or from the internal memory of other adsp-21160x dsps. external devices, including other adsp-21160x dsps, must assert rdl for reading from the low word of processor internal memory. in a multiprocessing system, rdl is driven by the bus master. rdl has a 20 k internal pull-up resistor that is enabled on the processor with id2C0 = 00x. rdh i/o/t memory read high strobe. rdh is asserted whenever adsp-21160x reads from the high word of external memory or from the internal memory of other adsp-21160x dsps. external devices, including other adsp-21160x dsps, must assert rdh for reading from the high word of adsp-21160x internal memory. in a multiprocessing system, rdh is driven by the bus master. rdh has a 20 k internal pull-up resistor that is enabled on the processor with id2C0 = 00x. wrl i/o/t memory write low strobe. wrl is asserted when adsp-21160x writ es to the low word of external memory or internal memory of other adsp-21160x dsps. external devices must assert wrl for writing to adsp-21160x dsps low word of inte rnal memory. in a multiprocessing system, wrl is driven by the bus master. wrl has a 20 k internal pull-up resistor that is enabled on the processor with id2C0 = 00x. wrh i/o/t memory write high strobe. wrh is asserted when adsp-21160x writes to the high word of external memory or internal memory of other adsp-21160x dsps. external devices must assert wrh for writing to adsp-21160x dsps high word of internal memory. in a multiprocessing system, wrh is driven by the bus master. wrh has a 20 k internal pull-up resistor that is enabled on the processor with id2C0 = 00x.
rev. b | page 12 of 60 | february 2010 adsp-21160m/adsp-21160n page o/t dram page boundary. the processor asserts this pi n to an external dram controller, to signal that an external dram page boundary has been crosse d. dram page size must be defined in the processors memory control register (wait). dram can only be implemented in external memory bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing system, page is output by the bus master. a keeper latch on the dsps page pin maintains the output at the level it was last driven (only enabled on the processor with id2C0 = 00x). brst i/o/t sequential burst access. brst is asserted by ad sp-21160x or a host to indicate that data associated with consecutive addresses is being read or writte n. a slave device sample s the initial address and increments an internal address counter after each transfer. the incremented address is not pipelined on the bus. if the burst access is a read from the host to the processor, the processor automatically increments the address as long as brst is asserted. brst is asserted after the initial access of a burst transfer. it is asserted for every cycle after that, except for the last data request cycle (denoted by rdx or wrx asserted and brst negated). a keeper latch on the dsps brst pin maintains the input at the level it was last driven (only enabled on the processor with id2C0 = 00x). ack i/o/s memory acknowledge. external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. the adsp-21160x deasserts ack as an output to add wait states to a synchronous access of its intern al memory, by a synchronous host or another dsp in a multiprocessor configuration. ack has a 2 k internal pull-up resistor that is enabled on the processor with id2C0 = 00x. sbts i/s suspend bus and three-state. external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high-impedance state for the following cycle. if the adsp-21160x attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor and/or adsp-21 160x deadlock or used with a dram controller. irq2C0 i/a interrupt request lines. these are sampled on th e rising edge of clkin and may be either edge- triggered or level-sensitive. flag3C0 i/o/a flag pins. each is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. timexp o timer expired. asserted for four processor core clock (cclk) cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request. must be asserted by a host processor to request control of the adsp-21160x dsps external bus. when hbr is asserted in a multiprocessing system, the processor that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the processor places the address, data, select, and strobe lines in a high-impedance state. hbr has priority over all processor bus requests (br6C1 ) in a multiprocessing system. hbg i/o host bus grant. acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21160x until hbr is released. in a multiprocessing system, hbg is output by the processor bus master and is monitored by all others. after hbr is asserted, and before hbg is given, hbg will float for 1 t clk (1 clkin cycle). to avoid erroneous grants, hbg should be pulled up with a 20 k to 50 k external resistor. cs i/a chip select. asserted by host processor to se lect the adsp-21160x, for asynchronous transfer protocol. redy o (o/d) host bus acknowledge. the adsp-21160x de asserts redy (low) to add wait states to an asynchronous host access when cs and hbr inputs are asserted. dmar1 i/a dma request 1 (dma channel 11). asserted by external port devices to request dma services. dmar1 has a 20 k internal pull-up resistor that is en abled on the adsp-21160x with id2C0 = 00x. dmar2 i/a dma request 2 (dma channel 12). asserted by external port devices to request dma services. dmar2 has a 20 k internal pull-up resistor that is en abled on the adsp-21160x with id2C0 = 00x. table 3. pin function descriptions (continued) pin type function
adsp-21160m/adsp-21160n rev. b | page 13 of 60 | february 2010 id2C0 i multiprocessing id. determines which multiprocessing bus request (br1 Cbr6 ) is used by the adsp-21160x. id = 001 corresponds to br1 , id = 010 corresponds to br2 , and so on. use id = 000 or id = 001 in single-processor systems. these lines are a system configuration selection which should be hardwired or only changed at reset. dmag1 o/t dma grant 1 (dma channel 11). asserted by adsp-21160x to indicate that the requested dma starts on the next cycle. driven by bus master only. dmag1 has a 20 k internal pull-up resistor that is enabled on the adsp-21160x with id2C0 = 00x. dmag2 o/t dma grant 2 (dma channel 12). asserted by adsp-21160x to indicate that the requested dma starts on the next cycle. driven by bus master only. dmag2 has a 20 k internal pull-up resistor that is enabled on the adsp-21160x with id2C0 = 00x. br6C1 i/o/s multiprocessing bus requests . used by multiprocessing adsp-21160x dsps to arbitrate for bus mastership. an adsp-21160x only drives its own brx line (corresponding to the value of its id2C0 inputs) and monitors all others. in a multiproce ssor system with less than six adsp-21160x dsps, the unused brx pins should be pulled high; the processors own brx line must not be pulled high or low because it is an output. rpba i/s rotating priority bus arbitration select. when rp ba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed prio rity is selected. this signal is a system configu- ration selection which must be set to the same va lue on every adsp-21160x. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every processor. pa i/o/t priority access. asserting its pa pin allows an adsp-21160x bus slave to interrupt background dma transfers and gain access to the external bus. pa is connected to all adsp-21160x dsps in the system. if access priority is not required in a system, the pa pin should be left unconnected. pa has a 20 k internal pull-up resistor that is enab led on the adsp-21160x with id2C0 = 00x. dtx o data transmit (serial ports 0, 1). each dt pin has a 50 k internal pull-up resistor. drx i data receive (serial ports 0, 1). each dr pin has a 50 k internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k internal pull-up resistor. rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k internal pull-up resistor. tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). lxdat7C0 i/o link port data (link ports 0C5). each lxdat pin has a 50 k internal pull-down resistor that is enabled or disabled by the lpdr d bit of the lctl0C1 register. lxclk i/o link port clock (link ports 0C5). each lxclk pin has a 50 k internal pull-down resistor that is enabled or disabled by the lp drd bit of the lctl0C1 register. lxack i/o link port acknowledge (link ports 0C5). each lxack pin has a 50 k internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. eboot i eprom boot select. for a description of how this pin operates, see table 4 . this signal is a system configuration selection that should be hardwired. lboot i link boot. for a description of how this pin operates, see table 4 . this signal is a system configu- ration selection that should be hardwired. bms i/o/t boot memory select. serves as an output or input as selected with the eboot and lboot pins; see table 4 . this input is a system configuration selection that should be hardwired. clkin i local clock in. clkin is the adsp-21160x clock input. the adsp-21160x external port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency; it is program- mable at power-up. clkin may not be halted, chan ged, or operated below the specified frequency. clk_cfg3C0 i core/clkin ratio control. adsp-21160x core cl ock (instruction cycle) rate is equal to n x clkin where n is user-selectable to 2, 3, or 4, using the clk_cfg3C0 inputs. for clock configuration defini- tions, see the reset & clkin section of the system design chapter of the adsp-21160 sharc dsp hardware reference . table 3. pin function descriptions (continued) pin type function
rev. b | page 14 of 60 | february 2010 adsp-21160m/adsp-21160n clkout o/t local clock out. clkout is driven at the clkin frequency by the processor. this output can be three-stated by setting the cod bit in the syscon register. a keeper latch on the dsps clkout pin maintains the output at the level it was last driven (only enabled on the processor with id2-0 = 00x). do not use clkout in mult iprocessing systems; use clkin instead. reset i/a processor reset. resets the adsp-21160x to a known state and begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i test clock (jtag). provides a clock for jtag boundary scan. tms i/s test mode select (jtag). used to control the test state machine. tms has a 20 k internal pull-up resistor. tdi i/s test data input (jtag). provides serial data for the boundary scan logic. tdi has a 20 k internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i/a test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power- up or held low for proper operation of the adsp-21160x. trst has a 20 k internal pull-up resistor. emu o (o/d) emulation status. must be connected to the adsp-21160x emulator target board connector only. emu has a 50 k internal pull-up resistor. cif o/t core instruction fetch. signal is active low when an external instruction fetch is performed. driven by bus master only. three-state when host is bus master. cif has a 20 k internal pull-up resistor that is enabled on the adsp-21160x with id2C0 = 00x. v ddint p core power supply. nominally 2.5 v (adsp-21160m) or 1.9 v (adsp-21160n) dc and supplies the dsps core processor v ddext p i/o power supply. nominally 3.3 v dc. av dd p analog power supply. nominally 2.5 v (adsp-21160m) or 1.9 v (adsp-21160n) dc and supplies the dsps internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 8 . agnd g analog power supply return. gnd g power supply return. nc do not connect. reserved pins that must be left open and unconnected. table 4. boot mode selection eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1 (input) host processor 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 010 (input)reserved 1 1 x (input) reserved table 3. pin function descriptions (continued) pin type function
adsp-21160m/adsp-21160n rev. b | page 15 of 60 | february 2010 specifications operating conditionsadsp-21160m table 5 shows the recommended operating conditions for the adsp-21160m. specifications ar e subject to change without notice. table 5. operating conditionsadsp-21160m k grade unit parameter min max v ddint internal (core) supply voltage 2.37 2.63 v av dd analog (pll) supply voltage 2.37 2.63 v v ddext external (i/o) supply voltage 3.13 3.47 v t case case operating temperature 1 085oc v ih1 high level input voltage, 2 @ v ddext =max 2.2 v ddext +0.5 v v ih2 high level input voltage, 3 @ v ddext =max 2.3 v ddext +0.5 v v il low level input voltage ,2, 3 @ v ddext =min C0.5 +0.8 v 1 see environmental conditions on page 51 for information on thermal specifications. 2 applies to input and bidirectional pins: data63C0, addr31C0, rdx , wrx , ack, sbts , irq2C0 , flag3C0, hbg , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, pa , brst, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, and rclk1. 3 applies to input pins: clkin, reset , and trst .
rev. b | page 16 of 60 | february 2010 adsp-21160m/adsp-21160n electrical characteristicsadsp-21160m table 6 shows adsp-21160m electrical characteristics. these specifications are subject to change without notification. table 6. electrical characteristicsadsp-21160m parameter test conditions min max unit v oh high level output voltage 1 @ v ddext =min, i oh =C2.0 ma 2 2.4 v v ol low level output voltage 1 @ v ddext =min, i ol =4.0 ma 2 0.4 v i ih high level input current 3, 4, 5 @ v ddext =max, v in =v dd max 10 a i il low level input current 3 @ v ddext =max, v in =0 v 10 a i ilpu1 low level input current pull-up1 4 @ v ddext =max, v in =0 v 250 a i ilpu2 low level input current pull-up2 5 @ v ddext =max, v in =0 v 500 a i ozh three-state leakage current 6, 7, 8, 9 @ v ddext =max, v in =v dd max 10 a i ozl three-state leakage current 6 @ v ddext =max, v in =0 v 10 a i ozhpd three-state leakage current pull-down 9 @ v ddext =max, v in =v dd max 250 a i ozlpu1 three-state leakage current pull-up1 7 @ v ddext =max, v in =0 v 250 a i ozlpu2 three-state leakage current pull-up2 8 @ v ddext =max, v in =0 v 500 a i ozha three-state leakage current 10 @ v ddext =max, v in =v dd max 25 a i ozla three-state leakage current 10 @ v ddext =max, v in =0 v 4 ma i dd-inpeak supply current (internal) 11 t cclk =12.5 ns, v ddint =max 1400 ma i dd-inhigh supply current (internal) 12 t cclk =12.5 ns, v ddint =max 875 ma i dd-inlow supply current (internal) 13 t cclk =12.5 ns, v ddint =max 625 ma i dd-idle supply current (idle) 14 t cclk =12.5 ns, v ddint =max 400 ma ai dd supply current (analog) 15 @av dd =max 10 ma c in input capacitance 16, 17 f in =1 mhz, t case =25c, v in =2.5 v 4.7 pf 1 applies to output and bidirectio nal pins: data63C0, addr31C0, ms3C0 , rdx , wrx , page, clkout, ack, flag3C0, timexp, hbg , redy, dmag1 , dmag2 , br6C1 , pa , brst, cif , dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, bms , tdo, and emu . 2 see output drive currents on page 47 for typical drive current capabilities. 3 applies to input pins: sbts , irq2C0 , hbr , cs , id2C0, rpba, eboot, lboot, clkin, reset , tck, and clk_cfg3-0. 4 applies to input pins with internal pull-ups: dr0, and dr1. 5 applies to input pins with internal pull-ups: dmarx , tms, tdi, and trst . 6 applies to three-statable pins: data63C0, ad dr31C0, page, clkout, a ck, flag3C0, redy, hbg , bms , br6C1 , tfsx, rfsx, and tdo. 7 applies to three-statable pins with interna l pull-ups: dtx, tclkx, rclkx, and emu . 8 applies to three-statable pins with internal pull-ups: ms3C0 ,rdx , wrx , dmagx , pa , and cif . 9 applies to three-statable pins with interna l pull-downs: lxdat7C0, lxclk, and lxack. 10 applies to ack pulled up internally with 2 k during reset or id2C0 = 00x. 11 the test program used to measure i dd-inpeak represents worst-case processor operatio n and is not sustainable under normal appl ication conditions. actual internal power measurements made using typical a pplications are less than specified. for more information, see power dissipation on page 47 . 12 i dd-inhigh is a composite average based on a range of high activity code. for more information, see power dissipation on page 47 . 13 i dd-inlow is a composite average based on a range of low activity code. for more information, see power dissipation on page 47 . 14 idle denotes adsp-21160m state d uring execution of idle instruc tion. for more information, see power dissipation on page 47 . 15 characterized, but not tested. 16 applies to all signal pins. 17 guaranteed, but not tested.
adsp-21160m/adsp-21160n rev. b | page 17 of 60 | february 2010 operating conditionsadsp-21160n table 7 shows recommended operating conditions for the adsp-21160n. these specificatio ns are subject to change without notice. table 7. operating conditionsadsp-21160n c grade k grade unit parameter min max min max v ddint internal (core) supply voltage 1.8 2.0 1.8 2.0 v av dd analog (pll) supply voltage 1.8 2.0 1.8 2.0 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v t case case operating temperature 1 C 40 +100 0 85 oc v ih1 high level input voltage, 2 @ v ddext =max 2.0 v ddext +0.5 2.0 v ddext +0.5 v v ih2 high level input voltage, 3 @ v ddext =max 2.0 v ddext +0.5 2.0 v ddext +0.5 v v il low level input voltage ,2, 3 @ v ddext =min C0.5 +0.8 C0.5 +0.8 v 1 see environmental conditions on page 51 for information on thermal specifications. 2 applies to input and bidirectional pins: data63C0, addr31C0, rdx , wrx , ack, sbts , irq2C0 , flag3C0, hbg , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, pa , brst, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, and rclk1. 3 applies to input pins: clkin, reset , and trst .
rev. b | page 18 of 60 | february 2010 adsp-21160m/adsp-21160n electrical characteristicsadsp-21160n table 8 shows the electrical characteri stics. note that these spec- ifications are subject to ch ange without notification. table 8. electrical characteristicsadsp-21160n parameter test conditions min max unit v oh high level output voltage 1 @ v ddext =min, i oh =C2.0 ma 2 2.4 v v ol low level output voltage 1 @ v ddext =min, i ol =4.0 ma 2 0.4 v i ih high level input current 3, 4, 5 @ v ddext =max, v in =v dd max 10 a i il low level input current 3 @ v ddext =max, v in =0 v 10 a i ihc clkin high level input current 6 @ v ddext = max, v in = v ddext max 25 a i ilc clkin low level input current 6 @ v ddext = max, v in = 0 v 25 a i ikh keeper high load current 7 @ v ddext = max, v in = 2.0 v C250 C50 a i ikl keeper low load current 7 @ v ddext = max, v in = 0.8 v 50 200 a i ikh-od keeper high overdrive current 7, 8, 9 @ v ddext = max C300 a i ikl-od keeper low overdrive current 7, 8, 9 @ v ddext = max 300 a i ilpu1 low level input current pull-up1 4 @ v ddext =max, v in =0 v 250 a i ilpu2 low level input current pull-up2 5 @ v ddext =max, v in =0 v 500 a i ozh three-state leakage current 10, 11, 12, 13 @ v ddext =max, v in =v dd max 10 a i ozl three-state leakage current 10 @ v ddext =max, v in =0 v 10 a i ozhpd three-state leakage current pull-down 13 @ v ddext =max, v in =v dd max 250 a i ozlpu1 three-state leakage current pull-up1 11 @ v ddext =max, v in =0 v 250 a i ozlpu2 three-state leakage current pull-up2 12 @ v ddext =max, v in =0 v 500 a i ozha three-state leakage current 14 @ v ddext =max, v in =v dd max 25 a i ozla three-state leakage current 14 @ v ddext =max, v in =0 v 4 ma i dd-inpeak supply current (internal) 15 t cclk =10.0 ns, v ddint =max 960 ma i dd-inhigh supply current (internal) 16 t cclk =10.0 ns, v ddint =max 715 ma i dd-inlow supply current (internal) 17 t cclk =10.0 ns, v ddint =max 550 ma i dd-idle supply current (idle) 18 t cclk =10.0 ns, v ddint =max 450 ma ai dd supply current (analog) 9 @av dd =max 10 ma c in input capacitance 19, 20 f in =1 mhz, t case =25c, v in =2.5 v 4.7 pf 1 applies to output and bidirectional pins: data63C0, addr31C0, ms3C0 , rdx , wrx , page, clkout, ack, flag3C0, timexp, hbg , redy, dmag1 , dmag2 , br6C1 , pa , brst, cif , dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, bms , tdo, and emu . 2 see output drive currents 47 for typical drive current capabilities. 3 applies to input pins: sbts , irq2C0 , hbr , cs , id2C0, rpba, eboot, lboot, clkin, reset , tck, and clk_cfg3-0. 4 applies to input pins with internal pull-ups: dr0, and dr1. 5 applies to input pins with internal pull-ups: dmarx , tms, tdi, and trst . 6 applies to clkin only. 7 applies to all pins with keep er latches: addr31C0, data 63C0, page, brst, and clkout. 8 current required to switch from kept h igh to low, or from kept low to high. 9 characterized, but not tested. 10 applies to three-statable pin s: data63C0, addr31 C0, page, clkout, ack, flag3C0, redy, hbg , bms , br6C1 , tfsx, rfsx, and tdo. 11 applies to three-statable pins with interna l pull-ups: dtx, tclkx, rclkx, and emu . 12 applies to three-statable pins with internal pull-ups: ms3C0 ,rdx , wrx , dmagx , pa , and cif . 13 applies to three-statable pins with interna l pull-downs: lxdat7C0, lxclk, and lxack. 14 applies to ack pulled up internally with 2 k during reset or id2C0 = 00x. 15 the test program used to measure i dd-inpeak represents worst-case processor operatio n and is not sustainable under normal appl ication conditions. actual internal power measurements made using typical a pplications are less than specified. for more information, see power dissipation on page 47 . 16 i dd-inhigh is a composite average based on a range of high activity code. for more information, see power dissipation on page 47 . 17 i dd-inlow is a composite average based on a range of low activity code. for more information, see power dissipation on page 47 . 18 idle denotes adsp-21160n state du ring execution of idle instruc tion. for more information, see power dissipation on page 47 . 19 applies to all signal pins. 20 guaranteed, but not tested.
adsp-21160m/adsp-21160n rev. b | page 19 of 60 | february 2010 absolute maximum ratings stresses greater than those listed in table 9 (adsp-21160m) and table 10 (adsp-21160n) may cause permanent da mage to the device. these are stress rating s only; functional operation of the device at these or any other conditions greater than those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity package information the information presented in figure 7 provides details about the package branding fo r the adsp-21160m/adsp-21160n processor. for a complete listin g of product availability, see ordering guide on page 58 . table 9. absolute maxi mum ratingsadsp-21160m parameter rating internal (core) supply voltage (v ddint ) C0.3 v to +3.0 v analog (pll) supply voltage (a vdd ) C0.3 v to +3.0 v external (i/o) supply voltage (v ddext ) C0.3 v to +4.6 v input voltage C0.5 v to v ddext + 0.5 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c table 10. absolute maximum ratingsadsp-21160n parameter rating internal (core) supply voltage (v ddint ) C0.3 v to +2.3 v analog (pll) supply voltage (a vdd ) C0.3 v to +2.3 v external (i/o) supply voltage (v ddext ) C0.3 v to +4.6 v input voltage C0.5 v to v ddext + 0.5 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c esd (electrostatic discharge sensitive device) charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. figure 7. typical package brand table 11. package brand information brand key field description a adsp-21160 model (m or n) t temperature range pp package type z rohs compliant designation cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n s a #yyww country_of_ori g in ad s p-21160a tppz-cc
rev. b | page 20 of 60 | february 2010 adsp-21160m/adsp-21160n timing specifications the adsp-21160x dsps internal cl ock switches at higher fre- quencies than the system input clock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsps internal clock (the clock source for the exte rnal port logic and i/o pads). the adsp-21160x dsps internal clock (a multiple of clkin) provides the clock signal for timing internal memory, processor core, link ports, serial ports, an d external port (as required for read/write strobes in asynchrono us access mode). during reset, program the ratio between the dsps internal clock frequency and external (clkin) clock frequency with the clk_cfg3C0 pins. even though the internal cl ock is the clock source for the external port, the external port clock always switches at the clkin frequency. to determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (tdivx/rdivx for the serial ports and lxclkd 1C0 for the link ports). note the following definitions of various clock periods that are a function of clkin and the appropriate ratio control: ?t cclk = (t ck ) / cr ?t lclk = (t cclk ) lr ?t sclk = (t cclk ) sr where: ? lclk = link port clock ?sclk = serial port clock ?t ck = clkin clock period ?t cclk = (processor) core clock period ?t lclk = link port clock period ?t sclk = serial port clock period ? cr = core/clkin ratio (2, 3, or 4:1, determined by clk_cfg3C0 at reset) ? lr = link port/core clock ratio (1, 2, 3, or 4:1, determined by lxclkd) ? sr = serial port/core clock ratio (wide range, determined by clkdiv) use the exact timing informatio n given. do not attempt to derive parameters from the addi tion or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 33 on page 49 under test conditions for voltage ref- erence levels. switching characteristics specif y how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to en sure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to si gnals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. during processor reset (reset pin low) or software reset (srst bit in syscon register = 1), deassertion (ms3C0 , hbg , dmagx , rdx , wrx , cif , page, brst) and three-state (flag3-0, lxclk, lxack, lxdat7-0, ack, redy, pa , tfsx, rfsx, tclkx, rclkx, dtx, bms , tdo, emu , data) timings differ. these occur asynchronously to clkin, and may not meet the specifications published in the timing require- ments and switching characteristics tables. the maximum delay for deassertion and three-state is one t ck from reset pin asser- tion low or setting the srst bit in syscon. during reset the dsp will not respond to sbts , hbr , and mms accesses. hbr asserted before reset will be recognized, but an hbg will not be returned by the dsp until after reset is deasserted and the dsp has completed bus synchronization. unless otherwise noted, all timing specifications ( timing requirements and switching characteristics ) listed on pages 21 through 46 apply to both adsp-21160m and adsp-21160n. power-up sequencing for power-up sequencing, see table 12 and figure 8 . during the power-up sequence of the dsp, differences in the ramp-up rates and activation time between the two power supplies can cause current to flow in the i/o esd pr otection circuitry. to prevent this damage to the esd diode protection circuitry, analog devices recommends including a bootstrap schottky diode (see figure 9 ). the bootstrap schottky diode connected between the v ddint and v ddext power supplies protects the adsp-21160x from partially powering the v ddext supply. including a schottky diode will shorten the delay betw een the supply ramps and thus prevent damage to the esd diode pr otection circuitry. with this technique, if the v ddint rail rises ahead of the v ddext rail, the schottky diode pulls the v ddext rail along with the v ddint rail.
adsp-21160m/adsp-21160n rev. b | page 21 of 60 | february 2010 table 12. power-up sequencing parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd clkin running after valid v ddint /v ddext 1 0 200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 3 s switching characteristics t corerst dsp core reset deasserted after reset deasserted 4096t ck 3, 4 ms 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their v ddint and v ddext rails. voltage ramp rates can vary from microseconds to hundreds of milliseconds, depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal after meeting worst-case start-up timing of oscillators. refer to your oscillato r manufacturers data sheet for start-up time. 3 based on clkin cycles. 4 corerst is an internal signal only. the 40 96 cycle count is dependent on t srst specification. if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 8. power-up sequencing clkin reset t r s tvdd v ddext v ddint t ivddevdd t clkvdd t clkr s t t pllr s t t corer s t clk_cfg 3 -0 corerst
rev. b | page 22 of 60 | february 2010 adsp-21160m/adsp-21160n clock input for clock input, see table 13 and figure 10 . figure 9. dual voltage schottky diode v ddext voltage regulator v ddint voltage regulator ad s p-21160x v ddext v ddint table 13. clock input parameter adsp-21160m 80 mhz adsp-21160n 100 mhz unit min max min max timing requirements t ck clkin period 25 80 20 80 ns t ckl clkin width low 10.5 40 7.5 40 ns t ckh clkin width high 10.5 40 7.5 40 ns t ckrf clkin rise/fall (0.4 vC2.0 v) 3 3 ns t cclk core clock period 12.5 40 10 30 ns figure 10. clock input clkin t ckh t ckl t ck
adsp-21160m/adsp-21160n rev. b | page 23 of 60 | february 2010 reset for reset, see table 14 and figure 11 . table 14. reset parameter min max unit timing requirements t wrst reset pulsewidth low 1 4t ck ns t srst reset setup before clkin high 2 8ns 1 applies after the power-up sequence is comp lete. at power-up, the proces sors internal phase-locked l oop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). 2 only required if multiple adsp-211 60x dsps must come out of reset synchronous to clkin with program counters (pc) equal. not re quired for multiple adsp-21160x dsps comm unicating over the shared bus (through the external port), because the bus arbit ration logic automatically synchronizes itself after reset. figure 11. reset clkin reset t wrst t srst
rev. b | page 24 of 60 | february 2010 adsp-21160m/adsp-21160n interrupts for interrupts, see table 15 and figure 12 . timer for timer, see table 16 and figure 13 . table 15. interrupts parameter min max unit timing requirements t sir irq2C0 setup before clkin high 1 6ns t hir irq2C0 hold after clkin high 1 0ns t ipw irq2C0 pulsewidth 2 2+t ck ns 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. figure 12. interrupts clkin irq2?0 t ipw t sir t hir table 16. timer parameter min max unit switching characteristic t dtex clkin high to timexp 1 19ns 1 for adsp-21160m, specif ication is 7 ns, maximum. figure 13. timer clkin timexp t dtex t dtex
adsp-21160m/adsp-21160n rev. b | page 25 of 60 | february 2010 flags for flags, see table 17 and figure 14 . table 17. flags parameter min max unit timing requirements t sfi flag3C0 in setup before clkin high 1 4ns t hfi flag3C0 in hold after clkin high 1 1ns t dwrfi flag3C0 in delay after rdx /wrx low 1, 2 10 ns t hfiwr flag3C0 in hold after rdx /wrx deasserted 1 0ns switching characteristics t dfo flag3C0 out delay after clkin high 9 ns t hfo flag3C0 out hold after clkin high 1 ns t dfoe clkin high to flag3C0 out enable 1 ns t dfod clkin high to flag3C0 out disable 3 t ck Ct cclk +5 ns 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. 2 for adsp-21160m, specific ation is 12 ns, maximum. 3 for adsp-21160m, specif ication is 5 ns, maximum. figure 14. flags clkin flag3?0 out flag output clkin rdx flag input flag3?0 in t dfo t hfo t dfo t dfod t dfoe t sfi t hfi t hfiwr t dwrfi wrx
rev. b | page 26 of 60 | february 2010 adsp-21160m/adsp-21160n memory readbus master use these specifications for asynchronous interfacing to memories (and memory-mapped pe ripherals) without reference to clkin accept for the ack pin requirements listed in note 6 of table 18 . these specifications apply when the adsp-21160x is the bus master accessing exte rnal memory space in asynchro- nous access mode. table 18. memory readbus master parameter min max unit timing requirements t dad address, cif , selects delay to data valid 1, 2, 3 t ck C0.25t cclk C8.5+w ns t drld rdx low to data valid 1, 4 t ck C0.5t cclk +w ns t hda data hold from address, selects 5 0ns t sds data setup to rdx high 1 8ns t hdrh data hold from rdx high 5 1ns t daak ack delay from address, selects 2, 6 t ck C0.5t cclk C12+w ns t dsak ack delay from rdx low 6 t ck C0.75t cclk C11+w ns t sakc ack setup to clkin 6 0.5t cclk +3 ns t hakc ack hold after clkin 1 ns switching characteristics t drha address, cif , selects hold after rdx high 0.25t cclk C1+h ns t darl address, cif , selects to rdx low 2 0.25t cclk C3 ns t rw rdx pulsewidth t ck C0.5t cclk C1+w ns t rwr rdx high to wrx , rdx , dmagx low 0.5t cclk C1+hi ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). 1 data delay/setup: user must meet t dad , t drld , or t sds . 2 the falling edge of msx , bms is referenced. 3 for adsp-21160m, specification is t ck C0.25t cclk C11+w ns, maximum. 4 for adsp-21160m, spec ification is 0.75t ck C11+w ns, maximum. 5 data hold: user must meet t hda or t hdrh in asynchronous access mode. see example system hold time calculation on page 49 for the calculation of hold times given capacitive and dc loads. 6 for asynchronous access, ack is sampled only after the programmed wait states for the access have been counted. for the first c lkin cycle of a new external memory access, ack must be driven low (deasserted) by t daak , t dsak , or t sakc . for the second and subseque nt cycles of an asynchronou s external memory access, the t sakc and t hakc must be met for both assertion and deassertion of ack signal.
adsp-21160m/adsp-21160n rev. b | page 27 of 60 | february 2010 figure 15. memory readbus master ack data t darl t rw t dad t daak t hdrh t hda t rwr t drld t drha t d s ak t s d s t s akc t hakc clkin addre ss msx , bms, rd wr , dmag cif
rev. b | page 28 of 60 | february 2010 adsp-21160m/adsp-21160n memory writebus master use these specifications for asynchronous interfacing to memories (and memory-mapped pe ripherals) without reference to clkin except for the ack pin requirements listed in note 1 of table 19 . these specifications apply when the adsp-21160x is the bus master accessing exte rnal memory space in asynchro- nous access mode. table 19. memory writebus master parameter min max unit timing requirements t daak ack delay from address, selects 1, 2 t ck C0.5t cclk C12+w ns t dsak ack delay from wrx low 1 t ck C0.75t cclk C11+w ns t sakc ack setup to clkin 1 0.5t cclk +3 ns t hakc ack hold after clkin 1 1ns switching characteristics t dawh address, cif , selects to wrx deasserted 2 t ck C0.25t cclk C3+w ns t dawl address, cif , selects to wrx low 2 0.25t cclk C3 ns t ww wrx pulsewidth t ck C0.5t cclk C1+w ns t ddwh data setup before wrx high 3 t ck C0.5t cclk C1+w ns t dwha address hold after wrx deasserted 0.25t cclk C1+h ns t dwhd data hold after wrx deasserted 0.25t cclk C1+h ns t datrwh data disable after wrx deasserted 4 0.25t cclk C 2+h 0.25t cclk +2+h ns t wwr wrx high to wrx , rdx , dmagx low 0.5t cclk C1+hi ns t ddwr data disable before wrx or rdx low 0.25t cclk C1+i ns t wde wrx low to data enabled C0.25t cclk C1 ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). hi = t ck (if an address hold cycle or bus idle cycle occurs , as specified in wait register; otherwise hi = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). 1 for asynchronous access, ack is sampled only after the programmed wait states for the access have been counted. for the first c lkin cycle of a new external memory access, ack must be driven low (deasserted) by t daak or t dsak or t sakc . for the second and subsequent cycles of an asynchronous external memory access, the t sakc and t hakc must be met for both assertio n and deassertion of ack signal 2 the falling edge of msx , bms is referenced. 3 for adsp-21160m, specification is t ck C0.25t cclk C12.5+w ns, minimum. 4 see example system hold time calculation on page 49 for calculation of hold times given capacitive and dc loads.
adsp-21160m/adsp-21160n rev. b | page 29 of 60 | february 2010 figure 16. memory writebus master rd , dmag clkin ack data wr cif msx , bms, addre ss dawl daak d s ak wde dawh ww s akc ddwh datrwh dwhd hakc dwha wwr ddwr t t t t t t t t t t t t t t
rev. b | page 30 of 60 | february 2010 adsp-21160m/adsp-21160n synchronous read/writebus master see table 20 and figure 17 . use these specifications for interfac- ing to external memory system s that require clkinrelative timing or for accessing a sla ve adsp-21160x (in multiprocessor memory space). these synchron ous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see memory readCbus master on page 26 and memory writeCbus master on page 28 ). when accessing a slave adsp- 21160x, these switching charac- teristics must meet the slav es timing requirements for synchronous read/writes (see synchronous read/writeCbus slave on page 32 ). the slave adsp-21160x must also meet these (bus master) timing requiremen ts for data and acknowledge setup and hold times. table 20. synchronous read/writebus master parameter min max unit timing requirements t ssdati data setup before clkin 5.5 ns t hsdati data hold after clkin 1 ns t sackc ack setup before clkin 0.5t cclk +3 ns t hackc ack hold after clkin 1 ns switching characteristics t daddo address, msx , bms , brst, cif delay after clkin 10 ns t haddo address, msx , bms , brst, cif hold after clkin 1.5 ns t dpgo page delay after clkin 1.5 11 ns t drdo rdx high delay after clkin 0.25t cclk C 1 0.25t cclk +9 ns t dwro wrx high delay after clkin 0.25t cclk C 1 0.25t cclk +9 ns t drwl rdx /wrx low delay after clkin 0.25t cclk C 1 0.25t cclk +9 ns t ddato data delay after clkin 1 0.25t cclk +9 ns t hdato data hold after clkin 1.5 ns t dackmo ack delay after clkin 2, 3 39ns t ackmtr ack disable before clkin 2 C3 ns t dckoo clkout delay after clkin 4 0.5 5 ns t ckop clkout period t ck C1 t ck 5 +1 ns t ckwh clkout width high t ck /2 C 2 t ck /2+2 2 ns t ckwl clkout width low t ck /2 C 2 t ck /2+2 2 ns 1 for adsp-21160m, specific ation is 12.5 ns, maximum. 2 applies to broadcast write, master precharge of ack. 3 for adsp-21160m, spec ification is 0.25t cclk +3 ns (minimum) and .25t cclk +9 ns (maximum). 4 for adsp-21160m, specif ication is 2 ns, minimum. 5 applies only when the dsp drives a bus operation; clkout held inactive or three-state otherwise. for more information, see the system design chapter in the adsp-21160 sharc dsp hardware reference .
adsp-21160m/adsp-21160n rev. b | page 31 of 60 | february 2010 figure 17. synchronous read/writebus master clkin clkout addre ss msx ,br s t, cif ack (in) page rdx data (out) wrx data (in) write cycle read cycle t drwl t h s dati t ss dati t drdo t dwro t hdato t ddato t drwl t dckoo t ckop t ckwl t haddo t dpgo t s ackc t hackc t daddo t ckwh ack (out) t dackmo t ackmtr
rev. b | page 32 of 60 | february 2010 adsp-21160m/adsp-21160n synchronous read/writebus slave see table 21 and figure 18 . use these specifications for adsp-21160x bus master accesses of a slaves iop registers or internal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements. table 21. synchronous read/writebus slave parameter min max unit timing requirements t saddi address, brst setup before clkin 5 ns t haddi address, brst hold after clkin 1 ns t srwi rdx /wrx setup before clkin 5 ns t hrwi rdx /wrx hold after clkin 1 ns t ssdati data setup before clkin 5.5 ns t hsdati data hold after clkin 1 ns switching characteristics t ddato data delay after clkin 1 0.25 t cclk + 9 ns t hdato data hold after clkin 1.5 ns t dackc ack delay after clkin 10 ns t hacko ack hold after clkin 1.5 ns 1 for adsp-21160m, specific ation is 12.5 ns, maximum. figure 18. synchronous read/writebus slave clkin address ack data (out) write access data (in) read access t saddi t haddi t dackc t hacko t hrwi t srwi t ddato t hdato t srwi t hrwi t hsdati t ssdati wrx rdx brst
adsp-21160m/adsp-21160n rev. b | page 33 of 60 | february 2010 multiprocessor bus request and host bus request see table 22 and figure 19 . use these specifications for passing of bus mastership between mu ltiprocessing adsp-21160x dsps (brx ) or a host processor, both synchronous and asynchronous (hbr , hbg ). table 22. multiprocessor bus request and host bus request parameter min max unit timing requirements t hbgrcsv hbg low to rdx /wrx /cs valid 1 6.5 + t ck + t cclk C 12.5cr ns t shbri hbr setup before clkin 2 6ns t hhbri hbr hold after clkin 2 1ns t shbgi hbg setup before clkin 6 ns t hhbgi hbg hold after clkin high 1 ns t sbri brx , pa setup before clkin 9 ns t hbri brx , pa hold after clkin high 1 ns t srpbai rpba setup before clkin 6 ns t hrpbai rpba hold after clkin 2 ns switching characteristics t dhbgo hbg delay after clkin 7 ns t hhbgo hbg hold after clkin 3 1.5 ns t dbro brx delay after clkin 8 ns t hbro brx hold after clkin 1.5 ns t dpaso pa delay after clkin, slave 8 ns t trpas pa disable after clkin, slave 1.5 ns t dpamo pa delay after clkin, master 0.25t cclk +9 ns t patr pa disable before clkin, master 4 0.25t cclk C5.5 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 5, 6 0.5t ck +1.0 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 5, 7 t ck +15 ns t ardytr redy (a/d) disable from cs or hbr high 5 11 ns 1 for adsp-21160m, specific ation is 19 ns, maximum. 2 only required for recognition in the current cycle. 3 for adsp-21160m, specif ication is 2 ns, maximum. 4 for adsp-21160m, spec ification is 0.25t ck C5 ns, minimum. 5 (o/d) = open drain, (a/d) = active drive. 6 for adsp-21160m, specification is 0.5t ck ns, maximum. 7 for adsp-21160m, specification is t ck +25 ns, maximum.
rev. b | page 34 of 60 | february 2010 adsp-21160m/adsp-21160n figure 19. multiprocessor bus request and host bus request rpba redy (o/d) redy (a/d) o/d = open drain, a/d = active drive t srpbai clkin (out) (out) t hhbg o t hbro t trpas t patr t hrpbai t hbri t sbri t shbgi t hhbgi t dpaso t db r o t dh b g o t hhbri t sh b r i t drdycs t trdyhg t hbgrcsv t ardytr t dpamo hbr hbg brx pa hb g br x , pa hbg rdx wr x cs (out) (master) pa (out) (s la v e) (in) (i n) hrb cs (o ut)
adsp-21160m/adsp-21160n rev. b | page 35 of 60 | february 2010 asynchronous read/writehost to adsp-21160x use these specifications ( table 23 , table 24 , figure 20 , and figure 21 ) for asynchronous host processor accesses of an adsp-21160x, after the host has asserted cs and hbr (low). after hbg is returned by the adsp -21160x, the host can drive the rdx and wrx pins to access the adsp-21160x dsps internal memory or iop registers. hbr and hbg are assumed low for this timing. table 23. read cycle parameter min max unit timing requirements t sadrdl address setup/cs low before rdx low 0 ns t hadrdh address hold/cs hold low after rdx 2ns t wrwh rdx /wrx high width 5 ns t drdhrdy rdx high delay after redy (o/d) disable 0 ns t drdhrdy rdx high delay after redy (a/d) disable 0 ns switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rdx low 1 11 ns t rdyprd redy (o/d) or (a/d) low pulsewidth for read 2 t ck C 4 ns t hdarwh data disable after rdx high 3 1.5 6 ns 1 for adsp-21160m, specif ication is 7 ns, minimum. 2 for adsp-21160m, specification is t ck ns, minimum. 3 for adsp-21160m, specif ication is 2 ns, minimum. table 24. write cycle parameter min max unit timing requirements t scswrl cs low setup before wrx low 0 ns t hcswrh cs low hold after wrx high 0 ns t sadwrh address setup before wrx high 6 ns t hadwrh address hold after wrx high 2 ns t wwrl wrx low width 1 t cclk +1 ns t wrwh rdx /wrx high width 5 ns t dwrhrdy wrx high delay after redy (o/d) or (a/d) disable 0 ns t sdatwh data setup before wrx high 5 ns t hdatwh data hold after wrx high 4 ns switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wrx /cs low 11 ns t rdypwr redy (o/d) or (a/d) low pulsewidth for write 2 5.75 + 0.5t cclk ns 1 for adsp-21160m, specif ication is 7 ns, minimum. 2 for adsp-21160m, specif ication is 12 ns, minimum
rev. b | page 36 of 60 | february 2010 adsp-21160m/adsp-21160n figure 20. asynchronous readhost to adsp-21160x figure 21. asynchronous writehost to adsp-21160x read cycle redy (o/d) rdx addre ss / cs data (out) redy (a/d) t s adrdl t drdyrdl t wrwh t hadrdh t hdarwh t rdyprd t drdhrdy t s datrdy o/d = open drain, a/d = active drive redy (o/d) wrx write cycle data (in) addre ss redy (a/d) cs t s datwh t hdatwh t wwrl t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy t s adwrh t s c s wrl t hc s wrh
adsp-21160m/adsp-21160n rev. b | page 37 of 60 | february 2010 three-state timingbus master, bus slave see table 25 and figure 22 . these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts pin. this timing is applicable to bus mast er transition cycles (btc) and host transition cycles (htc) as well as the sbts pin. table 25. three-state timing bus master, bus slave parameter min max unit timing requirements t stsck sbts setup before clkin 6 ns t htsck sbts hold after clkin 1 2ns switching characteristics t miena address/select enable after clkin 1.5 9 ns t miens strobes enable after clkin 2 1.5 9 ns t mienhg hbg enable after clkin 1.5 9 ns t mitra address/select disable after clkin 3 0.5 9 ns t mitrs strobes disable after clkin 2, 4, 5 0.25t cclk C4 0.25t cclk +1.5 ns t mitrhg hbg disable after clkin 6 0.5 8 ns t daten data enable after clkin 7, 8 0.25t cclk +1 0.25t cclk +7 ns t dattr data disable after clkin 7, 9 0.5 5 ns t acken ack enable after clkin 7 1.5 9 ns t acktr ack disable after clkin 7 1.5 5 ns t cdcen clkout enable after clkin 10 0.5 9 ns t cdctr clkout disable after clkin t cclk C3 t cclk +1 ns t atrhbg address, msx disable before hbg low 11 1.5t ck C6 1.5t ck + 5 ns t strhbg rdx , wrx , dmagx disable before hbg low 11 t ck + 0.25t cclk C6 t ck + 0.25t cclk + 5 ns t ptrhbg page disable before hbg low 11 t ck C6 t ck + 5 ns t btrhbg bms disable before hbg low 11 0.5t ck C6.5 0.5t ck + 1.5 ns t menhbg memory interface enable after hbg high 12, 13 t ck C5 t ck +6 ns 1 for adsp-21160m, specif ication is 1 ns, minimum. 2 strobes = rdx , wrx , and dmagx . 3 for adsp-21160m, spec ification is 0.25t cclk C1 ns (minimum) and 0.25t cclk +4 ns (maximum). 4 if access aborted by sbts , then strobes disable before clkin [0.25t cclk + 1.5 (min.), 0.25t cclk + 5 (max.)] 5 for adsp-21160m, spec ification is 0.25t cclk ns (maximum). 6 for adsp-21160m, specificat ion is 3.5 ns (minimum). 7 in addition to bus master transition cycles, these specs al so apply to bus master and bus slave synchronous read/write. 8 for adsp-21160m, specif ication is 1.5 ns (minimum) and 10 ns (maximum). 9 for adsp-21160m, specification is 1.5 ns (minimum). 10 for adsp-21160m, specification is 0.5 ns (minimum). 11 not specified for adsp-21160m. 12 memory interface = address, rdx , wrx , msx , page, dmagx , and bms (in eprom boot mode). 13 for adsp-21160m, specification is t ck +5 ns (maximum).
rev. b | page 38 of 60 | february 2010 adsp-21160m/adsp-21160n figure 22. three-state timi ngbus master, bus slave clkin sbts ack memory interface hbg memory interface = addre ss , rdx , wrx , msx ,page, dmagx. bms (in eprom boot mode) clkout data memory interface t menhbg t mitra, t mitr s , t mitrhg t s t s ck t ht s ck t dattr t daten t acktr t acken t cdctr t cdcen t miena, t mien s , t mienhg t atrhbg t s trhbg t ptrhbg t btrhbg
adsp-21160m/adsp-21160n rev. b | page 39 of 60 | february 2010 dma handshake see table 26 and figure 23 . these specifications describe the three dma handshake modes. in all three modes, dmarx is used to initiate transfers. for handshake mode, dmagx con- trols the latching or enabling of data externally. for external handshake mode, the data tran sfer is controlled by the addr31C0, rdx , wrx , page, ms3C0 , ack, and dmag x signals. for paced master mode, the data transfer is controlled by addr31C0, rdx , wrx , ms3C0 , and ack (not dmagx ). for paced master mode, the me mory read-bus master, mem- ory write-bus master, and sy nchronous read/write-bus master timing specifications for addr31C0, rdx , wrx , ms3C0 , page, data63C0, and ack also apply. table 26. dma handshake parameter min max unit timing requirements t sdrc dmarx setup before clkin 1 3ns t wdr dmarx width low (nonsynchronous) 2, 3 0.5t cclk +2.5 ns t sdatdgl data setup after dmagx low 4, 5 t ck C0.5t cclk C7 ns t hdatidg data hold after dmagx high 2 ns t datdrh data valid after dmarx high 4, 6 t ck +3 ns t dmarll dmarx low edge to low edge 7 t ck ns t dmarh dmarx width high 2, 8 0.5t cclk +1 ns switching characteristics t ddgl dmagx low delay after clkin 0.25t cclk +1 0.25t cclk +9 ns t wdgh dmagx high width 0.5t cclk C1+hi ns t wdgl dmagx low width t ck C0.5t cclk C1 ns t hdgc dmagx high delay after clkin t ck C0.25t cclk +1.5 t ck C0.25t cclk +9 ns t vdatdgh data valid before dmagx high 9 t ck C0.25t cclk C8 t ck C0.25t cclk +5 ns t datrdgh data disable after dmagx high 10 0.25t cclk C 3 0.25t cclk +1.5 ns t dgwrl wrx low before dmagx low C1.5 2 ns t dgwrh dmag x low before wrx high t ck C0.5t cclk C2+w ns t dgwrr wrx high before dmagx high 11 C1.5 2 ns t dgrdl rdx low before dmagx low C1.5 2 ns t drdgh rdx low before dmagx high t ck C0.5t cclk C2+w ns t dgrdr rdx high before dmagx high 11 C1.5 2 ns t dgwr dmagx high to wrx , rdx , dmagx low 0.5t cclk C2+hi ns t dadgh address/select valid to dmagx high 12 15.5 ns t ddgha address/select hold after dmagx high 1 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if data bus idle cycle occurs, as specif ied in wait register; otherwise hi = 0). 1 only required for recognition in the current cycle. 2 maximum throughput using dmarx / dmagx handshaking equals t wdr + t dmarh = (0.5t cclk +1) + (0.5t cclk +1)=10.0 ns (100 mhz). this throughput limit applies to non-synchronous access mode only. 3 for adsp-21160m, specification is t cclk +4.5 ns, minimum. 4 t sdatdgl is the data setup requirement if dmarx is not being used to ho ld off completion of a wr ite. otherwise, if dmarx low holds off completion of the write, the data can be driven t datdrh after dmarx is brought high. 5 for adsp-21160m, spec ification is 0.75t cclk C7 ns, maximum. 6 for adsp-21160m, specification is t clk +10 ns, maximum. 7 use t dmarll if dmarx transitions synchronous with clkin. otherwise, use t wdr and t dmarh . 8 for adsp-21160m, specification is t cclk +4.5 ns, minimum. 9 t vdatdgh is valid if dmarx is not being used to hold off completion of a read. if dmarx is used to prolong the read, then t vdatdgh =t ck C 0.25t cclk C8+(nt ck ) where n equals the number of extra cycles that the access is prolonged. 10 see example system hold time calculation on page 49 for calculation of hold times given capacitive and dc loads. 11 this parameter appl ies for synchronous access mode only. 12 for adsp-21160m, specification is 18 ns, minimum.
rev. b | page 40 of 60 | february 2010 adsp-21160m/adsp-21160n figure 23. dma handshake clkin t s drc dmarx data data rdx wrx t wdr t s drc t dmarh t dmarll t hdgc t wdgh t ddgl dmagx t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t s datdgl * memory read bu s ma s ter, memory write bu s ma s ter, or s ynchronou s read/write bu s ma s ter timing s pecification s for addr 3 1?0, rdx , wrx , ms3C0 and ack al s oapplyhere. (external device to external memory) (external memory to external device) tran s fer s between ad s p-2116x internal memory and external device tran s fer s between external device and external memory * (external hand s hake mode) t ddgha addr msx t dadgh t wdgl (from external drive to ad s p-2116x) (from ad s p-2116x to external drive)
adsp-21160m/adsp-21160n rev. b | page 41 of 60 | february 2010 link portsreceive, transmit for link ports, see table 27 , table 28 , figure 24 , and figure 25 . calculation of link receiver data setup and hold, relative to link clock, is required to determ ine the maximum allowable skew that can be introduced in the transmission path, between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata, relative to lclk (setup skew = t lclktwh minimum C t dldch Ct sldcl ). hold skew is the maximum delay that can be introduced in lclk, relative to ldata (hold skew = t lclktwl minimum + t hldch Ct hldcl ). cal- culations made directly from sp eed specifications result in unrealistically small skew times, because they include multiple tester guardbands. note that there is a two-cycle effect latency between the link port enable instruction and th e dsp enabling the link port. table 27. link portsreceive parameter min max unit timing requirements t sldcl data setup before lclk low 2.5 ns t hldcl data hold after lclk low 1 3ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 2 4ns t lclkrwh lclk width high 3 4ns switching characteristics t dlalc lack low delay after lclk high 4, 5 917ns 1 for adsp-21160m, specific ation is 2.5 ns, minimum. 2 for adsp-21160m, specif ication is 6 ns, minimum. 3 for adsp-21160m, specif ication is 6 ns, minimum. 4 lack goes low with t dlalc relative to rise of lclk after first nibble, but does not go low if the receiv ers link buffer is not about to fill. 5 for adsp-21160m, specific ation is 12 ns, minimum. figure 24. link portsreceive lclk ldat(7:0) lack (out) receive in t sldcl t hldcl t lclkrwh t dlalc t lclkrwl t lclkiw
rev. b | page 42 of 60 | february 2010 adsp-21160m/adsp-21160n table 28. link portstransmit parameter min max unit timing requirements t slach lack setup before lclk high 14 ns t hlach lack hold after lclk high C2 ns switching characteristics t dldch data delay after lclk high 4 ns t hldch data hold after lclk high C2 ns t lclktwl lclk width low 1 0.5t lclk C 0.5 0.5t lclk +0.5 ns t lclktwh lclk width high 2 0.5t lclk C0.5 0.5t lclk +0.5 ns t dlaclk lclk low delay after lack high 3 0.5t lclk +4 3/2t lclk +11 ns 1 for adsp-21160m, specification is 0.5t lclk C1.5 ns (minimum) and 0.5t lclk +1.5 ns (maximum). 2 for adsp-21160m, specification is 0.5t lclk C1.5 ns (minimum) and 0.5t lclk +1.5 ns (maximum). 3 for adsp-21160m, specification is 0.5t lclk +5 ns (minimum) and 3t lclk +11 ns (maximum). figure 25. link portstransmit lclk ldat(7:0) lack (in) the t slach requirement applies to the rising edge of lclk only for the first nibble/byte transmitted. transmit last nibble/byte transmitted first nibble/byte transmitted lclk inactive (high) out t dldch t hldch t lclktwh t lclktwl t slach t hlach t dlaclk
adsp-21160m/adsp-21160n rev. b | page 43 of 60 | february 2010 serial ports for serial ports, see table 29 , table 30 , table 31 , table 32 , table 33 , table 34 , table 35 , figure 26 , and figure 27 . to deter- mine whether communication is possible between two devices at clock speed n, the following sp ecifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 29. serial portsexternal clock parameter min max unit timing requirements t sfse tfs/rfs setup before tclk/rclk 1 3.5 ns t hfse tfs/rfs hold after tclk/rclk 1 4ns t sdre receive data setup before rclk 1 1.5 ns t hdre receive data hold after rclk 1, 2 6.5 ns t sclkw tclk/rclk width 3 8ns t sclk tclk/rclk period 2t cclk ns 1 referenced to sample edge. 2 for adsp-21160m, specif ication is 4 ns, minimum. 3 for adsp-21160m, specific ation is 14 ns, minimum. table 30. serial portsinternal clock parameter min max unit timing requirements t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 8ns t hfsi tfs/rfs hold after tclk/rclk 1, 2 t cclk /2 + 1 ns t sdri receive data setup before rclk 1 6.5 ns t hdri receive data hold after rclk 1 3ns 1 referenced to sample edge. 2 for adsp-21160m, specif ication is 1 ns, minimum table 31. serial portsexternal or internal clock parameter min max unit switching characteristics t dfse rfs delay after rclk (internally generated rfs) 1 13 ns t hofse rfs hold after rclk (i nternally generated rfs) 1 3ns 1 referenced to drive edge. table 32. serial portsexternal clock parameter min max unit switching characteristics t dfse tfs delay after tclk (internally generated tfs) 1 13 ns t hofse tfs hold after tclk (internally generated tfs) 1 3ns t ddte transmit data delay after tclk 1 16 ns t hdte transmit data hold after tclk 1 0ns 1 referenced to drive edge.
rev. b | page 44 of 60 | february 2010 adsp-21160m/adsp-21160n table 33. serial portsenable and three-state parameter min max unit switching characteristics t ddten data enable from external tclk 1 4ns t ddtte data disable from external tclk 1 10 ns t ddtin data enable from internal tclk 1 0ns t ddtti data disable from internal tclk 1 3ns 1 referenced to drive edge. table 34. serial portsinternal clock parameter min max unit switching characteristics t dfsi tfs delay after tclk (internally generated tfs) 1 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 1 C1.5 ns t ddti transmit data delay after tclk 1 7.5 ns t hdti transmit data hold after tclk 1 0ns t sclkiw tclk/rclk width 2 0.5t sclk C1.5 0.5t sclk +1.5 ns 1 referenced to drive edge. 2 for adsp-21160m, specification is 0.5t sclk C2.5 ns (minimum) and 0.5t sclk +2 ns (maximum) figure 26. serial portsexternal late frame sync drive sample drive tclk tfs dt drive sample drive late external tfs external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs 1st bit 2nd bit t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t hofse/i t sfse/i t ddte/i tddtenfs t ddtlfse t hdte/i
adsp-21160m/adsp-21160n rev. b | page 45 of 60 | february 2010 table 35. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external tf s or external rfs with mce = 1, mfd = 0 1 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 1.0 ns 1 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . figure 27. serial ports dt dt drive edge drive edge drive edge drive edge tclk / rclk tclk (int) tclk / rclk tclk (ext) rclk rfs dr drive edge sample edge data receive? internal clock data receive? external clock rclk rfs dr drive edge sample edge note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. tclk tfs dt drive edge sample edge tclk tfs dt drive edge sample edge data transmit? internal clock data transmit? external clock note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddtte t ddten t ddtti t ddtin t sdri t hdri t sfsi t hfsi t dfse t hofse t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse t ddti t hdti t sfsi t hfsi t sclkiw t dfsi t hofsi t ddte t hdte t sfse t hfse t dfse t sclkw t hofse
rev. b | page 46 of 60 | february 2010 adsp-21160m/adsp-21160n jtag test access port and emulation for jtag test access po rt and emulation, see table 36 and figure 28 . table 36. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 7ns t hsys system inputs hold after tck low 1 18 ns t trstw trst pulsewidth 4t ck ns switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 30 ns 1 system inputs = data63C0, addr31C0, rdx , wrx , ack, sbts , hbr , hbg , cs , dmar1 , dmar2 , br6C1 , id2C0, rpba, irq2C0 , flag3C0, pa , brst, dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, eboot, lboot, bms , clkin, and reset . 2 system outputs = data63C0, addr31C0, ms3C0 , rdx , wrx , ack, page, clkout, hbg , redy, dmag1 , dmag2 , br6C1 , pa , brst, cif , flag3C0, timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat7C0, lxclk, lxack, and bms . figure 28. jtag test ac cess port and emulation tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21160m/adsp-21160n rev. b | page 47 of 60 | february 2010 output drive currentsadsp-21160m figure 29 shows typical iCv characteri stics for the output driv- ers of the adsp-21160m. the cu rves represent the current drive capability of the output drivers as a function of output voltage. output drive currentsadsp-21160n figure 30 shows typical iCv characteri stics for the output driv- ers of the adsp-21160n. the curv es represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two components: one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. using the current specifications (i dd-inpeak , i dd-inhigh , i dd-inlow , and i dd-idle ) from electrical characteristicsadsp-21160m on page 16 and electrical characteristicsadsp-21160n on page 18 and the current-versus-operation information in table 37 , engineers can estimate the adsp-21160x dsps internal power supply (v ddint ) input current for a specific application, according to the formula: % peak i dd - inpeak % high i dd - inhigh % low i dd - inlow + % peak i dd - idle = i ddint the external component of total power dissipation is caused by the switching of output pins . its magnitude depends on: ? the number of output pins that switch during each cycle ( o ) ? the maximum frequency at which they can switch ( f ) ?their load capacitance ( c ) ?their voltage swing ( v dd ) and is calculated by: p ext = o c v dd 2 f the load capacitance should in clude the processors package capacitance (c in ). the switching frequenc y includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can sw itch on each cycle. example for adsp-21160n: estimate p ext with the following assumptions: ? a system with one bank of external data memory asynchronous ram (64-bit) ? four 64k 16 ram chips are used, each with a load of 10 pf ? external data memory writes oc cur every other cycle, a rate of 1/(2 t ck ), with 50% of the pins switching ? the bus cycle time is 50 mhz (t ck = 20 ns). the p ext equation is calculated fo r each class of pins that can drive, as shown in table 38 . a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + p int + p pll where: ?p ext is from table 38 ?p int is i ddint 1.9 v, using the calculation i ddint listed in power dissipation on page 47 ?p pll is ai dd 1.9 v, using the value for ai dd listed in elec- trical characteristicsadsp-21160m on page 16 and electrical characteristicsadsp-21160n on page 18 figure 29. adsp-21160m typical drive currents figure 30. adsp-21160n typical drive currents source (v ddext )voltage?v ?120 03.5 0.5 1 1.5 2 2.5 3 s o u r c e ( v d d e x t ) c u r r e n t ? m a ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 v ddext = 3.47v, 0c v ddext = 3.3v, 25c v ddext =3.13v, 85c v ddext =3.47v,0c v ddext = 3.3v, 25c v ddext = 3.13v, 85c sweep (v ddext ) voltage ? v 03.5 0.5 1 1.5 2 2.5 3 s o u r c e ( v d d e x t ) c u r r e n t ? m a ?80 ?60 ?40 ?20 0 20 40 60 80 v ddext = 3.47v, ?45c v ddext =3.47v,?45c v ddext =3.3v,25c v ddext = 3.11v, 115c v oh v ddext = 3.11v, 115c v ddext =3.3v,25c v ol
rev. b | page 48 of 60 | february 2010 adsp-21160m/adsp-21160n note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pi ns are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions the test conditions for timing parameters appearing in adsp-21160x specifications on page 17 include output disable time, output enable time, and capacitive loading. output disable time output pins are considered to be disabled when they stop driv- ing, go into a high-impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation: t decay = (c l v)/i l the output disable time t dis is the difference between t measured and t decay as shown in figure 31 . the time t measured is the inter- val from when the reference signal switches to when the output voltage decays v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with v equal to 0.5 v. table 37. adsp-21160x operation types vs. input current operation peak activity 1 high activity 1 low activity 1 instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 2 per t ck cycle (dm 64 and pm 64) 1 per t ck cycle (dm 64) none internal memory dma 1 per 2 t cclk cycles 1 per 2 t cclk cycles none external memory dma 1 per external port cycle ( 64) 1 per external port cycle ( 64) none data bit pattern for core memory access and dma worst case random n/a 1 peak activity = i dd-inpeak , high activity = i dd-inhigh , and low activity = i dd-inlow . the state of the peyen bit (simd versus sisd mode) does not influe nce these calculations. 2 these assume a 2:1 core clock ratio. for more information on ratios and clocks (t ck and t cclk ), see the timing ratio definitions on page 20 . table 38. external power calcul ations (adsp-21160n example) pin type no. of pins % switching c f v dd 2 = p ext address 15 50 44.7 pf 24 mhz 10.9 v = 0.088 w ms0 1 0 44.7 pf 24 mhz 10.9 v = 0.000 w wrx 2 44.7 pf 24 mhz 10.9 v = 0.023 w data 64 50 14.7 pf 24 mhz 10.9 v = 0.123 w clkout 1 4.7 pf 48 mhz 10.9 v = 0.003 w p ext = 0.237 w figure 31. output enable/disable reference s ignal t di s output s tart s driving v oh (mea s ured) ? $ v v ol (mea s ured) + $ v t mea s ured v oh (mea s ured) v ol (mea s ured) 2.0v 1.0v high impedance s tate. te s t condition s cau s ethi s voltage to be approximately 1.5v output s top s driving t decay t ena
adsp-21160m/adsp-21160n rev. b | page 49 of 60 | february 2010 output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 31 ). if multiple pins (such as the data bus) ar e enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the adsp-21160x dsps output voltage and the input threshold for the device requiring the hold time. a typical v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 32 ). figure 34 , figure 35 , figure 37 , and figure 38 show how output rise ti me varies with capaci- tance. figure 36 and figure 39 graphically show how output delays and holds vary with load capacitance. (note that this graph or derating does not apply to output disable delays; see output disable time on page 48 .) the graphs of figure 37 , figure 38 , figure 39 , figure 40 , figure 41 , and figure 42 may not be linear outside the ranges shown. figure 32. equivalent device loading for ac measurements (includes all fixtures) figure 33. voltage reference levels for ac measurements (except output enable/disable) 1.5v 3 0pf to output pin 50 6 input or output 1.5v 1.5v figure 34. adsp-21160m typical output rise time (10%?90%, v ddext =max) vs. load capacitance figure 35. adsp-21160m typical output rise time (10%?90%, v ddext =min) vs. load capacitance load capacitance ? pf 20 0 0 50 100 150 200 30 10 5 25 15 r i s e a n d f a l l t i m e s ? n s rise time fall time y = 0.072781x +1.99 y = 0.086687x +2.18 load capacitance ? pf 20 0 0 250 50 100 150 200 10 5 25 15 tbd r i s e a n d f a l l t i m e s ? n s fall time y = 0.0834x +1.0653 y = 0.0813x +2.312 rise time
rev. b | page 50 of 60 | february 2010 adsp-21160m/adsp-21160n figure 36. adsp-21160m typical output delay or hold vs. load capacitance (at max case temperature) figure 37. adsp-21160n typical output rise time (20%C80%, v ddext =max) vs. load capacitance load capacitance ? pf 15 0 0 50 100 150 200 5 ?5 20 10 o u t p u t d e l a y o r h o l d ? n s y = 0.085526x ?3.87 load capacitance ? pf 0 0 50 100 150 200 r i s e a n d f a l l t i m e s ? n s 2 4 6 8 10 12 14 16 18 20 y = 0.0751x + 1.4882 y = 0.0716x + 2.9043 rise time fall time figure 38. adsp-21160n typical output rise time (20%?80%, v ddext =min) vs. load capacitance figure 39. adsp-21160n typical output delay or hold vs. load capacitance (at max case temperature) load capacitance ? pf 20 0 0 50 100 150 200 10 5 25 15 r i s e a n d f a l l t i m e s ? n s fall time y = 0.0834x + 1.0653 y = 0.0813x +2.312 rise time load capacitance ? pf 4 ?2 0 50 100 150 200 0 ?4 6 2 o u t p u t d e l a y o r h o l d ? n s y = 0.0716x ?3.9037 8 10 12
adsp-21160m/adsp-21160n rev. b | page 51 of 60 | february 2010 environmental conditions thermal characteristics the adsp-21160x dsps are provid ed in a 400-ball pbga (plas- tic ball grid ar ray) package. the adsp-21160x is specified for a case temperature ( t case ). to ensure that the t case data sheet specificat ion is not exceeded, a heatsink and/or an air flow source may be used. use the cen- terblock of ground pins (f or adsp-21160m, pbga balls: h8-13, j8-13, k8-13, l8-13, m8-13, n8-13; for adsp-21160n, pbga balls: f7-14, g7-14, h7-14, j7-14, k7-14, l7-14, m-14, n7-14, p7-14, r7-15) to provide thermal pathways to the printed circuit boards ground plane. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. ?t case = case temperature (measured on top surface of package) ? pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation). ? ca = value from table 39 . ? jb = 6.46c/w table 39. airflow over package versus ca airflow (linear ft./min.) 0 200 400 ca (c/w) 1 1 jc = 3.6 c/w 12.13 9.86 8.7 t case t amb pd ca () + =
rev. b | page 52 of 60 | february 2010 adsp-21160m/adsp-21160n 400-ball pbga pin configurations table 40 lists the pin assignments for the pbga package, and the pin configurations diagram in figure 40 (adsp-21160m) and figure 41 (adsp-21160n) show the pin assignment summary. table 40. 400-ball pbga pin assignments (see footnotes 1 and 2) pin name pin no. pin name pin no. pin name pin no. pin name pin no. data[14] a01 data[22] b01 data[24] c01 data[28] d01 data[13] a02 data[16] b02 data[18] c02 data[25] d02 data[10] a03 data[15] b03 data[17] c03 data[20] d03 data[8] a04 data[9] b04 data[11] c04 data[19] d04 data[4] a05 data[6] b05 data[7] c05 data[12] d05 data[2] a06 data[3] b06 data[5] c06 v ddext d06 tdi a07 data[0] b07 data[1] c07 v ddint d07 trst a08 tck b08 tms c08 v ddext d08 reset a09 emu b09 td0 c09 v ddext d09 rpba a10 irq2 b10 irq1 c10 v ddext d10 irq0 a11 flag3 b11 flag2 c11 v ddext d11 flag1 a12 flag0 b12 nc 1 c12 v ddext d12 timexp a13 nc 1 b13 nc c13 v ddint d13 nc 1 a14 nc b14 tclk1 c14 v ddext d14 nc a15 dt1 b15 dr1 c15 tfs0 d15 tfs1 a16 rclk1 b16 dr0 c16 l1dat[7] d16 rfs1 a17 rfs0 b17 l0dat[7] c17 l0clk d17 rclk0 a18 tclk0 b18 l0dat[6] c18 l0dat[3] d18 dt0 a19 l0dat[5] b19 l0ack c19 l0dat[1] d19 l0dat[4] a20 l0dat[2] b20 l0dat[0] c20 l1clk d20 data[30] e01 data[34] f01 data[38] g01 data[40] h01 data[29] e02 data[33] f02 data[35] g02 data[39] h02 data[23] e03 data[27] f03 data[32] g03 data[37] h03 data[21] e04 data[26] f04 data[31] g04 data[36] h04 v ddext e05 v ddext f05 v ddext g05 v ddext h05 v ddint e06 v ddint f06 v ddint g06 v ddint h06 v ddint e07 gnd f07 gnd g07 gnd h07 v ddint e08 gnd f08 gnd g08 gnd h08 v ddint e09 gnd f09 gnd g09 gnd h09 v ddint e10 gnd f10 gnd g10 gnd h10 gnd e11 gnd f11 gnd g11 gnd h11 v ddint e12 gnd f12 gnd g12 gnd h12 v ddint e13 gnd f13 gnd g13 gnd h13 v ddint e14 gnd f14 gnd g14 gnd h14 v ddint e15 v ddint f15 v ddint g15 v ddint h15 v ddext e16 v ddext f16 v ddext g16 v ddext h16 l1dat[6] e17 l1dat[4] f17 l1dat[2] g17 l2dat[5] h17 l1dat[5] e18 l1dat[3] f18 l2dat[6] g18 l2ack h18 l1ack e19 l1dat[0] f19 l2dat[4] g19 l2dat[3] h19 l1dat[1] e20 l2dat[7] f20 l2clk g20 l2dat[1] h20
adsp-21160m/adsp-21160n rev. b | page 53 of 60 | february 2010 data[44] j01 clk_cfg_0 k01 clkin l01 av dd m01 data[43] j02 data[46] k02 clk_cfg_1 l02 clk_cfg_3 m02 data[42] j03 data[45] k03 agnd l03 clkout m03 data[41] j04 data[47] k04 clk_cfg_2 l04 nc 2 m04 v ddext j05 v ddext k05 v ddext l05 v ddext m05 v ddint j06 v ddint k06 v ddint l06 v ddint m06 gnd j07 gnd k07 gnd l07 gnd m07 gnd j08 gnd k08 gnd l08 gnd m08 gnd j09 gnd k09 gnd l09 gnd m09 gnd j10 gnd k10 gnd l10 gnd m10 gnd j11 gnd k11 gnd l11 gnd m11 gnd j12 gnd k12 gnd l12 gnd m12 gnd j13 gnd k13 gnd l13 gnd m13 gnd j14 gnd k14 gnd l14 gnd m14 v ddint j15 v ddint k15 v ddint l15 v ddint m15 v ddext j16 v ddext k16 v ddext l16 v ddext m16 l2dat[2] j17 br6 k17 br2 l17 page m17 l2dat[0] j18 br5 k18 br1 l18 sbts m18 hbg j19 br4 k19 ack l19 pa m19 hbr j20 br3 k20 redy l20 l3dat[7] m20 nc n01 data[49] p01 data[53] r01 data[56] t01 nc n02 data[50] p02 data[54] r02 data[58] t02 data[48] n03 data[52] p03 data[57] r03 data[59] t03 data[51] n04 data[55] p04 data[60] r04 data[63] t04 v ddext n05 v ddext p05 v ddext r05 v ddext t05 v ddint n06 v ddint p06 v ddint r06 v ddint t06 gnd n07 gnd p07 gnd r07 v ddint t07 gnd n08 gnd p08 gnd r08 v ddint t08 gnd n09 gnd p09 gnd r09 v ddint t09 gnd n10 gnd p10 gnd r10 v ddint t10 gnd n11 gnd p11 gnd r11 v ddint t11 gnd n12 gnd p12 gnd r12 v ddint t12 gnd n13 gnd p13 gnd r13 v ddint t13 gnd n14 gnd p14 gnd r14 v ddint t14 v ddint n15 v ddint p15 gnd r15 v ddint t15 v ddext n16 v ddext p16 v ddext r16 v ddext t16 l3dat[5] n17 l3dat[2] p17 l4dat[5] r17 l4dat[3] t17 l3dat[6] n18 l3dat[1] p18 l4dat[6] r18 l4ack t18 l3dat[4] n19 l3dat[3] p19 l4dat[7] r19 l4clk t19 l3clk n20 l3ack p20 l3dat[0] r20 l4dat[4] t20 data[61] u01 addr[4] v01 addr[5] w01 addr[8] y01 data[62] u02 addr[6] v02 addr[9] w02 addr[11] y02 addr[3] u03 addr[7] v03 addr[12] w03 addr[13] y03 addr[2] u04 addr[10] v04 addr[15] w04 addr[16] y04 v ddext u05 addr[14] v05 addr[17] w05 addr[19] y05 v ddext u06 addr[18] v06 addr[20] w06 addr[21] y06 table 40. 400-ball pbga pin assignments (continued) (see footnotes 1 and 2) pin name pin no. pin name pin no. pin name pin no. pin name pin no.
rev. b | page 54 of 60 | february 2010 adsp-21160m/adsp-21160n v ddext u07 addr[22] v07 addr[23] w07 addr[24] y07 v ddext u08 addr[25] v08 addr[26] w08 addr[27] y08 v ddext u09 addr[28] v09 addr[29] w09 addr[30] y09 v ddext u10 id0 v10 id1 w10 addr[31] y10 v ddext u11 addr[1] v11 addr[0] w11 id2 y11 v ddext u12 ms1 v12 bms w12 brst y12 v ddext u13 cs v13 ms2 w13 ms0 y13 v ddext u14 rdl v14 cif w14 ms3 y14 v ddext u15 dmar2 v15 rdh w15 wrh y15 v ddext u16 l5dat[0] v16 dmag2 w16 wrl y16 l5dat[7] u17 l5dat[2] v17 lboot w17 dmag1 y17 l4dat[0] u18 l5ack v18 l5dat[1] w18 dmar1 y18 l4dat[1] u19 l5dat[4] v19 l5dat[3] w19 eboot y19 l4dat[2] u20 l5dat[6] v20 l5dat[5] w20 l5clk y20 1 for adsp-21160m, pin name and function is defined as v ddext . for adsp-21160n, pin name and functi on is defined as no connect (nc). 2 for adsp-21160n, pin name and function is de fined as gnd. for adsp-211 60m, pin name and function is defined as no connect (nc ). table 40. 400-ball pbga pin assignments (continued) (see footnotes 1 and 2) pin name pin no. pin name pin no. pin name pin no. pin name pin no.
adsp-21160m/adsp-21160n rev. b | page 55 of 60 | february 2010 figure 40. adsp-21160m 400-ball pbga pin configurations (bottom view, summary) use the center block of ground pins (pbga balls: h8-13, j8-13, k8-13, l8-13, m8-13, n8-13) to provide thermal pathways to your printed circuit board?s ground plane. v ddint v ddext gnd agnd av dd i/o signals key: no connection 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t 1 1
rev. b | page 56 of 60 | february 2010 adsp-21160m/adsp-21160n figure 41. adsp-21160n 400-ball pbga pin configurations (bottom view, summary) use the center block of ground pins (pbga balls: f7-14, g7-14, h7-14, j7-14, k7-14, l7-14, m7-14, n7-14, p7-14, r7-15) to provide thermal pathways to your printed circuit board?s ground plane. v ddint v ddext gnd agnd av dd i/o signals key: no connection 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t 1 1
adsp-21160m/adsp-21160n rev. b | page 57 of 60 | february 2010 outline dimensions the adsp-21160x processors are available in a 27 mm 27 mm, 400-ball pbga lead-free package. surface-mount design the following table is provided as an aide to pcb design. for industry-standard design recommendations, refer to ipc-7351, generic requirements fo r surface-mount design and land pattern standard . figure 42. 400-ball plastic grid array (pbga) (b-400) complian t to jedec standards ms-034-bal -2 (dimensions in millimeters) 0.90 0.75 0.60 ball diameter 0.70 0.60 0.50 0.60 0.55 0.50 2.49 2.32 2.15 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t 24.13 bsc top view detail a seating plane 1.19 1.17 1.15 0.20 max detail a 27.20 27.00 26.80 sq sq 1.27 bsc bottom view ball a1 indicator ball a1 pad corner coplanarity package ball attach type solder mask opening ball pad size 400-ball grid array (pbga) solder mask de fined (smd) 0.63 mm diameter 0.76 mm diameter
rev. b | page 58 of 60 | february 2010 adsp-21160m/adsp-21160n ordering guide model 1 1 z = rohs compliant part. temperature range instruction rate on-chip sram package description package option ADSP-21160MKBZ-80 0c to +85c 80 mhz 4m bits 400-ball plastic ball grid array (pbga) b-400 adsp-21160mkb-80 0c to +85c 80 mhz 4m bits 400-ball plastic ball grid array (pbga) b-400 adsp-21160ncbz-100 C40c to +100c 100 mhz 4m bits 400-ball plastic ball grid array (pbga) b-400 adsp-21160ncb-100 C40c to +100c 100 mhz 4m bits 400-ball plastic ball grid array (pbga) b-400 adsp-21160nkbz-100 0c to +85c 100 mhz 4m bits 400-ball plastic ball grid array (pbga) b-400 adsp-21160nkb-100 0c to +85c 100 mhz 4m bits 400-ball plastic ball grid array (pbga) b-400
adsp-21160m/adsp-21160n rev. b | page 59 of 60 | february 2010
rev. b | page 60 of 60 | february 2010 adsp-21160m/adsp-21160n ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02426-0-2/10(b)

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